The present invention relates to semiconductor devices, and, more particularly, to dynamic random access memories.
The development of large monolithic dynamic random access memories (dRAMs) has run into many problems, and one of the most important of these problems is that of shrinking the dRAM cell size without increasing the soft-error rate in order to pack more cells on a chip. Large dRAMs are silicon based and each cell typically includes a single MOS field effect transistor with its source connected to a storage capacitor, its drain connected to a bit line, and its gate connected to a word line; the cell operates by storing a charge on the capacitor for a logic 1 and not storing any charge for a logic 0. Traditionally the cell capacitor has been formed by an inversion layer separated from an overlying electrode by a thin oxide layer and from the substrate by a depletion layer. However, to maintain stable circuit operation the capacitance must be large enough to yield a sufficient signal to noise ratio, and this leads to large substrate area devoted to the capacitor. Further, such a MOS capacitor is vulnerable to charges generated in the substrate by alpha particles (a 5 MeV alpha particle can produce more than 200 femtocoulombs of hazardous electrons), noise injected from the substrate, pn junction leakage over the entire area of the capacitor, and subthreshold leakage of the cell transistor. A typical stored charge in a dRAM cell is 250 fC. For a five volt power supply this requires a storage capacitor of 50 fF; and with a storage oxide thickness of 150 A, a capacitor area of about 20 square microns is needed. This imposes a lower limit on the cell size if conventional two dimensional technology is used.
One approach to solve these problems appears in Jolly et al, A Dynamic RAM Cell in Recrystallized Polysilicon, 4 IEEE Elec. Dev.Lett. 8 (1983) and forms all basic elements of the cell, including both the access transistor and the charge storage capacitor, in a layer of beam recrystallized polysilicon deposited on an oxide layer on a silicon substrate. The bit line is contained in the recrystallized polysilicon layer, and turning on the transistor causes charge to flow into the storage region, which is composed of heavily doped, recrystallized polysilicon surrounded on the top, bottom, and three sides by thermally grown oxide. The storage capability is about twice that of a conventional capacitor of the same storage area since electrodes both above and below are separated from the storage region in the recrystallized polysilicon by thin oxides. In addition, the lower oxide isolates the storage region from any charge injected into the substrate either from surrounding circuitry or by alpha particles or other radiation generating soft errors. Further, thick oxide under the bit line and complete sidewall oxide isolation reduce the bit-line capacitance. However, even doubling the capacitance over the traditional design fails to sufficiently shrink the area occupied by the cell capacitor.
A second approach to shrinking dRAM cell size relies on a capacitor with plates extending into the substrate. This capacitor, called a corrugated capacitor, is described in H. Sunami et at, A Corrugated Capacitor Cell (CCC) for Megabit Dynamic MOS Memories, IEEE IEDM Tech Digest 806 (1982); H. Sunami et al, A Corrugated Capacitor Cell (CCC) for Megabit Dynamic MOS Memories, 4 IEEE Elec.Dev.Lett. 90 (1983); and K. Itoh et al, An Experimental 1 Mb DRAM with On-Chip Voltage Limiter, 1984 IEEE ISSCC Digest of Tech Papers 282. The corrugated capacitor extends about 2.5 microns into the silicon substrate. Fabrication proceeds as follows: Trenches are formed by ordinary reactive sputter etching with CCl.sub.4 gas using a CVD silicon dioxide film mask; a wet etch cleans up any dry etching damage and contaminations. After trench formation, a triple storage layer of silicon dioxide/silicon nitride/silicon dioxide is formed on the trench walls. Lastly, the trench is filled with LPCVD polysilicon. Use of the corrugated capacitor assertedly yields more than seven times the capacitance of the conventional cell, with a three micron by seven micron cell having a 60 fF storage capacitance.
A third approach to shrink the area occupied by the cell capacitor is similar to the approach described in the preceding paragraph and forms the capacitor in a trench. For example, E. Arai, Submicron MOS VLSI Process Technologies, IEEE IEDM Tech Digest 19 (1983); K. Minegishi et al, A Submicron CMOS Megabit Dynamic RAM Technology Using Doped Face Trench Capacitor cell, IEEE IEDM Tech Digest 319 (1983); and T. Morie et al, Depletion Trench Capacitor Technology for Megabit Level MOS dRAM, 4 IEEE Elec.Dev.Lett. 411 (1983) all describe a cell with a traditional design except for the capacitor which has been changed from plates parallel to the substrate to plates on the walls of a trench in the substrate. Such a trench capacitor permits large capacitance per unit area of substrate by simply using a deep trench. The capacitors described in these articles were fabricated as follows: Starting with (100) oriented, p-type, 4-5 ohm-cm resistivity silicon substrates, trench patterns with 0.4-1.0 micron width were formed by electron-beam direct writing. Trenches of 1-3 micron depth were then excavated by reactive ion etching with CBrF.sub.3 at a pressure of about 14 mTorr; the trench surfaces were cleared of RIE damage by an etch in a mixture of nitric, acetic, and hydrofluoric acids. PSG was then deposited by CVD using a PH.sub.3 /SiH.sub.4 /O.sub.2 gas system, the phosphorous diffused into the trench surface layers, and the PSG etched away by hydofluoric acid. SiO.sub.2 of 150-500 A was grown in dry O.sub.2 or CVD Si.sub.3 N.sub.4 was deposited 500 A thick on the trench walls. Lastly, the trenches were filled with LPCVD polysilicon. The capacitance per unit area of trench sidewall was comparable to the capacitance per unit area of a traditional capacitor; consequently, deep trench capacitors can shrink cell substrate area by enhancing the storage capacitor area per unit substrate area.
The use of trenches for isolation is also well known and has been extensively studied; for example, R. Rung et al, Deep Trench Isolated CMOS Device, IEEE IEDM Tech Digest 237 (1982); K. Cham et al, A Study of the Trench Inversion Problem in the Trench CMOS Technology, 4 IEEE Elec.Dev.Lett. 303 (1983); A. Hayasaka et al, U-Groove Isolation Technique for High Speed Bipolar VLSI's, IEEE IEDM Tech Digest 62 (1982); H. Goto et al, An Isolation Technology for High Performance Bipolar Memories--IOP-II, IEEE IEDM Tech Digest 58 (1982); T. Yamaguchi et al, High-Speed Latchup-Free 0.5-um-Channel CMOS Using Self-Aligned TiSi.sub.2 and Deep-Trench Isolation Technologies, IEEE IEDM Tech Digest 522 (1983); S. Kohyama et al, Directions in CMOS Technology, IEEE IEDM Tech Digest 151 (1983); and K. Cham et al, Characterization and Modeling of the Trench Surface Inversion Problem for the Trench Isolated CMOS Technology, IEEE IEDM Tech Digest 23 (1983). These isolation trenches are formed in a manner similar to that described for the trench and corrugated capacitors; namely, patterning (typically with oxide mask), RIE with CBrF.sub.3, CCl.sub.4, Cl.sub.2 --H.sub.2, CCl.sub.4 --O.sub.2, etc. excavation, thermal oxidation (plus LPCVD nitride) of the sidewalls, and filling with polysilicon.
However, the use of trench capacitors fails to fully solve the problems of shrinking dRAM cell size; namely, the cell still occupies a large substrate area for both the horizontally placed field effect transistor and a nearby vertically placed trench capacitor.